Multi-aperture core shift register



June 10, 1969 MULTI-APERTURE CORE SHIFT REGISTER Sheet Filed March 4,1963 INVENTORS KH. FRIELINGHAUS BY AND wasn/HTH THEIR AT'TOR'N E Y' jJunelo, 1969 K, H, PRIEUNGHA'US ET AL 3,449,729

MULTI-APERTURE CORE SHIFT` REGTSTER Sheet Filed March 4, 1965 INVENTORSK.H.FR|EL|NGHAUS BY AND WRSMTTH THEIR ATTORNEY- June 10, 1969 K. H.FRIELINGl-IAUS ET AI- MULTI-APERTURE CORE SHIFT REGISTER Z FDaFDOwHSheet 2m .DaPDOmH Filed March 4, 1963 E OAUHH N W H T R EGI O NM T WIS.T A. mw fm FD H.N Tu KA United States Patent O U.S. Cl. 340-174 18Claims ABSTRACT F THE DISCLOSURE A signal transfer circuit having aplurality of storage means each storage means being coupled to asubsequent storage means. A driver circuit is coupled to each storagemeans and is responsive to information stored in both the storage meansto which it is coupled and the next subsequent storage means. The driverinitiates the transfer of information from the storage means to whichthe driver is coupled to the next subsequent storage means when the nextsubsequent storage means is cleared. The information contained in thelast storage means is cleared when such information is accepted byapplication utilization circuitry.

This invention relates to signal transfer circuits and more particularlyto circuit means for transferring an input signal to utilization meanswhereby information applied to the circuit at a frequency rate abovethat which the utilization means is capable of accepting is temporarilystored in apertured magnetic cores until the utilization means is readyto accept the information.

In communication circuits, information is often received at varyingfrequency rates. However, the output circuit or utilization means isusually incapable of receiving information at greater than a 'fixedfrequency rate. Therefore, when bursts of energy at greater than thefixed frequency rate are transmitted to the utilization means, portionsof the signal are either erroneously received or entirely lost.

In other applications, information is often applied to a utilizationcircuit at a time when the circuit is incapable of accepting the appliedinformation. Under these circumstances, it is desirable to providestorage means for the signal whereby the signal may be stored until theutilization circuit again becomes capable of accepting the signal, atwhich time the signal is automatically transferred from the storagemeans to the utiliza-tion circuit.

Where information is transmitted in discrete bits, a storage means forretaining merely a single bit of information until the utilization meansis ready to accept the information is insufficient if many bits ofinformation are transmitted and the utilization means is incapable ofaccepting bits at a sufficient rate to permit no more than a single bitat a time to be applied to the storage means. Therefore, it is desirableto provide storage means capable of holding as many bits as may berequired to be stored prior to acceptance by the utilization means.

Storage means used in information transmittal circuits must transferinformation only at the proper times, for correct circuit operation.Such transfer may occur with use of solid state driver circuits, such astransistor circuits, which exhibit inherent leakage currents. Thisshortcoming may be overcome by use of driver circuits which present aninfinite impedance of the driver energy source except when transmittalof information is desired. Information transmittal from each storagemeans and driver circuit impedance control for each storage means can beachieved automatically in accordance with the remanent condition of eachsubsequent storage means.

Accordingly, one object of this invention is to provide a signaltransfer circuit comprising a plurality of storage stages wherebyinformation is automatically transferred from one clear storage stage tothe next subsequent clear storage stage, automatically, until it reachesa utilization means.

Another object is to provide a signal transfer circuit comprising aplurality of storage stages whereby information is automaticallytransferred from stage to stage until it reaches a stage prior to oneretaining stored information, wherein it is then retained.

Another object is to provide a signal transfer circuit comprising aplurality of information storage stages whereby information which isstored in one stage is automatically transferred to the next subsequentstorage stage only when the next subsequent stage becomes cleared.

Another object is to provide a signal transfer circuit utilizing aplurality of coupled storage stages and a separate driver coupled toeach storage stage for sensing the condition of the next subsequentstorage stage only When the subsequent stage is clear.

Another object is to provide a driver circuit for transferring storedinformation from a trst apertured magnetic core to a second aperturedmagnetic core when the second core is in the clear condition.

Another object is to provide a driver circuit for a rst aperturedmagnetic core whereby a capacitor discharge is coupled through a contactof a relay responsive to the remanent magnetic state of a subsequentmagnetic core for driving information out of the iirst magnetic corewhen the subsequent magnetic core is clear.

Ano-ther object of this invention is to provide a driver circuit forapertured magnetic cores whereby stored information in each core isrepresented by the set state of said core and a capacitor discharge isutilized for clearing the set core through contacts of relays responsiveto the set condition of said core and a clear condition of a subsequentcore.

The invention contemplates a plurality of storage means, each said meansbeing coupled to a subsequent storage means. A driver circuit is coupledto each storage means and is responsive to information stored in boththe storage means to which it is coupled and the next subsequent storagemeans. The driver initiates transfer of information from the storagemeans to which said driver is coupled, to the next subsequent storagemeans when the next subsequent storage means is cleared.

The foregoing and other objects and advantages of the invention willbecome apparent from the following detailed description when read inconjunction with the accompanying drawings, in which:

FIG. l is a functional block diagram of the novel signal transfercircuit.

FIG. 2 is a schematic diagram of a iirst embodiment of the novel signaltransfer circuit.

FIG. 3 is a schematic diagram of a second embodiment of the novel signaltransfer circuit.

FIG. 4 is a schematic diagram of a third embodiment of the novel signaltransfer circuit.

Turning now to FLIG. l for a general description of the system, there isshown a plurality of drivers, chosen for illustrative purposes only, tobe four, and a plurality of storage means, also chosen to be four. 'Eachdriver drives a single storage means. Each driver, moreover, isresponsive to the condition of the storage means to which it is coupledand to the next subsequent driver. Each storage means couples an inputsignal to the next subsequent storage means. Acceptance means arecoupled to the nal driver stage for control thereof in response eitherto an external signal or the condition of the output circuit. Means areprovided for coupling an input signal to the first storage means, andmeans are also provided for coupling a trigger signal to the rst driverstage.

In operation, assume an input signal is applied to the first storagemeans. When a trigger signal is thereafter applied to the first driver,the first driver being responsive to the condition of the second storagemeans via the second driver circuit senses that the second storage meansis clear. It therefore couples a drive signal to the first storagemeans, thus transferring information stored in the first storage meansto the second storage means. When the information is stored in thesecond storage means the second driver, being responsive to thecondition of the third storage means via the third driver, senses theclear condition of the third storage means and couples a drive pulse tothe second means, thereby transferring information stored in the secondstorage means to the third storage means. Similarly, the third driverthen transfers information stored in the third storage means to thefourth storage means. When information is stored in the fourth storagemeans, the fourth driver, being responsive to the condition of theacceptance means, provides an output signal from the fourth storagemeans containing the stored information upon receipt of a signal fromthe acceptance means. The acceptance means signal may be made to occurin response to the condition of the circuit to which the output signalis coupled, or it may be made to occur in response to an externallyapplied signal.

If no signal is provided from the acceptance means 'when information isstored in the fourth storage means, the fourth driver does not produce a`drive pulse for transferring the information to the output circuit. Ifthereafter a second signal should be applied to the first storage means,the signal is transferred as previously described, as far as the thirdstorage means. When information is stored in the third storage means,the third driver senses the condition of the fourth storage meansthrough the fourth driver. Since information is now stored in the fourthstorage means, it cannot accept information from the third storagemeans. Thus, the third driver does not produce a drive pulse fortransferring information from the third storage means to the fourthstorage means. Likerwise, a following input signal can only betransferre-d as far as the second storage means, wherein it is thenstored. A subsequent input signal can only be stored in the firststorage means.

'When the acceptance means provides a signal to the fourth driver, thefourth storage means receives a drive pulse from the fourth driver,thereby transferring its information to the output. The third driverthen senses the clear condition of the fourth storage means, andprovides a signal for driving information from the third storage meansto the fourth storage means. The third storage means is thereby clearedand the second driver then produces a transfer of information stored inthe second storage means to the third storage means in a similarfashion. Likewise, the first driver then produces a transfer ofinformation stored in the first storage means to the second storagemeans. This leaves the first storage means in a clear condition, readyto accept another input signal. Moreover, when the fourth driverreceives another signal from the acceptance means, the fourth storagemeans again produces an output, the third storage means transfers itsstored information to the fourth storage means, and the second storagemeans transfers its stored information to the third storage means. Thisleaves the first and second storage means in a clear condition, ready toaccept new information.

Although the system is shown having four storage means and four drivers,it should be obvious to those skilled in the art that any number ofstorage means and drivers may be used, as long as each storage means isdriven by a separate driver. Such system would be desirable where outputcircuit information can be accepted only at a predetermined rate, whileinformation is applied in bursts at a rate in excess of the rate atwhich the output circuit can accept the information.

Turning now to FIG. 2, for a detailed description of the firstembodiment of the invention, there is shown a plurality of storage meanscomprising apertured magnetic cores C1-C4. Each core has an output minoraperture 1-4, respectively. Moreover, cores C2-C4 have second outputminor aperture 5-7, respectively, through which a radio frequency signalfrom an R.F. signal generator 8 is coupled.

-Each of a plurality of relays R1-R4 is connected in series with a primesignal coupled respectively through output minor apertures 1-4 ofrespective cores C1-C4. Each output minor aperture 5 7 is coupled to arelay 1R5-R7, respectively, through series-connected capacitors 911,respectively. Diodes 12-'14 are parallel-connected across relays -RS-R7,respectively. Contacts 15417 of relays RS-IR7, respectively, areconnected in series with and control energization of relays RZ-R4,respectively, thereby also controlling priming of minor apertures 2-4 ofcores CK2-C4, respectively.

Each core C1-C4 is cleared by a signal passed through its major aperturefrom a front contact 18-21 of a relay lR1-R4, respectively. The clearpulse for each of cores C1'C4 respectively is applied through a Seriescircuit comprising a resistor 22-25, a forward-connected diode 26-29,and an inductor 30-33, respectively. The clear pulse for each of coresC1-C4 consists of current produced by the discharge of energy storagemeans comprising charged capacitors 34-37 respectively, through a backcontact 38, of relay R2, a back contact 39 of relay R3, a back contact40 of relay R4 and back contact 2'1 relay R4, respectively. Moreover,cores C1-C4 can receive their respective clear signals only when frontcontacts 18-21 of relays R1-aR4, respectively, are closed. Thus, eachclear pulse is passed through a circuit responsive to the remanentmagnetic state of a pair of adjacent cores.

The circuit permits relays R1-R4 to exhibit contact bounce in clearingthe cores without producing an adverse effect on circuit operation,since a pulse duration on the order to two microseconds is sufficient inorder clear any of cores (l1-C4. Tests have shown that the first reboundof a relay contact upon closing, due to closure impact reaction, doesnot occur until approximately five hundred microseconds after initialcontact closure has occurred; that is, once the contact is initiallyclosed, it remains closed for approximately five hundred microsecondsprior to bouncing open. Since a pulse of approximately two microsecondsduration is required to clear a core, the RLC time constants of resistor22, inductor 30 and capacitor 34, resistor 23, inductor 31 and capacitor35, resistor 24, inductor 32 and capacitor 36, and resistor 25, inductor33 and capacitor 37 are each chosen to produce an almost criticallydamped pulse which is far shorter in duration than five hundredmicroseconds. Such pulse duration is preferably chosen to be on theorder of two microseconds. Therefore, before the first bounce of therelay contact occurs, momentarily opening its circuit, the capacitorcoupled thereto is fully discharged, so that when the contact reclosesafter the first bounce, current cannot resume flowing through the majoraperture of the core through which the RLC circuit is coupled.

Each capacitor 34-37 acquires a charge through a resistor 41-44,respectively, in series with front contact 38 of relay R2, front contact39 of relay R3, front contact 40 of relay R4, and front contact 21 ofrelay R4, respectively. `Resistors 41-44 control the rate at whichcapacitors 34-37 charge, and thereby also serve to limit power supplysurges at the instant any of the capacitors begins to charge. Resistors22-25 and inductors 30-33 comprise pulse forming networks which shapethe discharge current waveforms of respective capacitors 34-37. Becauseof the short duration of pulses provided by capacitors 34-37, the pulseforming networks provide high output impedances which cause thecapacitors to appear as constant current sources during the intervals inwhich they provide pulses to the cores. Diodes 26-29 serve to eliminateany negative current overshoot through the clear circuits which iscreated in the event the current pulses through the clear circuits areslightly underdamped, as evidenced by a slight oscillation at the end ofeach of the current pulses.

Input information is coupled to core C1 in a fashion to alter theremanent magnetic state of the core through the leg between the majoraperture and output minor aperture 1. Output information from the legloutside the minor aperture of core C1 is coupled to core C2 in afashion to alter the remanent magnetic state of core C2 through the legbetween the major aperture and output minor aperture 2. Outputinformation is coupled from the leg outside output minor aperture 2 orcore C2 to core C3 in a fashion to alter the remanent magnetic state ofcore C3 in the leg between the major aperture and output minor aperture3. Output information is coupled from the leg outside output minoraperture 3 of core C3 to core C4 in a fashion to alter the remanentmagnetic state of the core in the leg between the major aperture andoutput minor aperture 4. Output information is coupled from the legoutside output minor aperture 4 of core C4 to a utilization means 45,which comprises any circuit or device requiring information of the formapplied to the novel coupling circuit.

When input current is applied to a multi-aperture core so as to threadthe leg located -between the major aperture and a minor aperture, thecore is switched to its set state. When the core is thereafterdestructively cleared, no output pulse is produced on the input, or setwinding, since the magnetic polarity in the leg between the major andminor apertures reverses only when the core is switched from the clearto the set state and from the set to the primed state, as is well-knownin the art. Thus, undesirable back transfer of pulses is avoided duringclearing of the core. Moreover, since priming is accomplished ywith aslow rise time direct current, the core is switched slowly from the setto the primed state, thus minimizing back transfer of pulses during thepriming operation.

Acceptance means 46 is coupled between the capacitor 37 and contact 21of relay R4, and may be any circuit controlling discharge of capacitor37 through contact 21, such as a gating circuit, a switch, a relaycontact, etc. The acceptance means may be made responsive either to anexternal control signal, or to the utilization means. In this respect, adotted line is shown coupling the utilization means to the acceptancemeans, indicating control of the acceptance means in this embodiment isin re sponse to the condition of the utilization means.

Each of the relays R5R7 is energized during the interval in which thecore coupled to the relay is set. This energization is achieved by meansof radio frequency energy induced in the circuit coupling the relay tothe core, by the signal from R.F. signal generator 8. Thus, when theinduced signal polarity is in the forward conducting direction of thediode connected in parallel with the relay, the capacitor acquires acharge. When the induced signal polarity reverses, current flows throughthe relay rather than the diode, since current liow direction is now inthe reverse conducting direction of the diode. Moreover, the voltagestored on the capacitor adds to the voltage produced from the outputminor aperture of the core, so that a large voltage is produced acrossthe relay. The relay then energizes and remains energized as long as thecore to which it is coupled remains set.

In operation, assume that no information is stored in the transfercircuit. Under such circumstances, cores C1, C2, C3 and 'C4 are clear.Capacitor 34 is fully charged through resistor 41 and back contacts 18and 38 of relays R1 and R2, respectively. Likewise, capacitor 35 isfully charged through resistor 42 and back contacts 19 and 39 of relayR2 and R3, respectively, capacitor 36 is fully charged through resistor43 and back contacts 20 and -40 of relays R3 and R4, respectively, andcapacitor 37 is fully charged through resistor 44, back contact 21 ofrelay R4 and acceptance means 46.

Assume now that an input signal is applied to the input terminals of thetransfer circuit. This causes core C1 to become set. Assume that next apositive trigger pulse is applied to the trigger terminal of thecircuit, momentarily energizing relay R1. Although the trigger circuitis herein depicted as receiving an external trigger pulse, the relay R1energizing pulse could alternatively be obtained automatically when core`C1 becomes set, in `a fashion similar to that for energizing relays R2,R3 and R4 from relays R5, R6 and R7, respectively, when cores C2, C3 andC4, respectively, are set.

Triggering of relay R1 serves to prime minor aperture 1 of core C1 witha show rise time direct current, due to the large inductance of therelay winding. Since a finite time interval exists between energizationof the relay and closing of its front contacts, core C1 is primed priorto closing of front contact 18. This provides a discharge path forcapacitor 34 through back contact 38 of relay R2 and front contact 18 ofrelay R1 through the major aperture of core C1. The capacitor dischargecauses core C1 to clear, producing an output pulse on the coupling loopthrough minor aperture 1 which sets core C2. Upon setting of core C2relay R5 becomes energized, closing its front contact 15 and therebypriming minor aperture 2 of core C2. Moreover, relay R2 energizes,closing its front contacts 19 and 38. Front contact 38 permits capacitor34 to again resume charging. Closing of front contact 19 permitscapacitor 35 to discharge through back contact 39 of relay R3 and frontcontact 19 of relay R2, through the major aperture of core C2, therebyclearing the core and producing an output pulse on the coupling loopthreading minor aperture 2 of core C2, in turn setting core C3. Uponclearing of core C2, relay R5 deenergizes, deenergizing relay R2.

When core C3 becomes set, relay R6 energizes, thereby energizing relayR3 yand priming minor aperture 3 of core C3. Front contact 20 of relayR3 then closes, permitting capacitor 36 to discharge through backcontact 40 of relay R4 and front contact 20 of relay R3, through themajor aperture of core C3. This clears core C3, causing relay R6 todeenergize and core C4 to become set. When core C4 becomes set, relay R7energizes, causing minor aperture 4 of core C4 to become primed andrelay R4 to become energized, closing its front Contact 21. Assuming theacceptance means is in condition to permit passage of the signal fromthe transfer circuit to the utilization means, capacitor 37 dischargesthrough the acceptance means and front contact 21 of relay R4, throughthe major aperture of core C4, causing an output signal to be producedon the coupling loop joining minor aperture 4 and utilization means 4S.Thus, the utilization means receives the signal initially applied to theinput terminals of the transfer circuit. Furthermore, when core C4clears, relay R7 deenergizes. The transfer circuit once again has noinformation stored therein, and is prepared to accept a new inputsignal.

Assume now that when the input signal is coupled through the circuit tocore C4, the acceptance means iS not conditioned to permit transfer ofthe charge stored on capacitor 37 through the major aperture of core C4.A single bit of information is therefore stored in core C4, and cannotbe transferred to the utilization means until the acceptance meanscompletes the circuit from capacitor 37 to front contact 21 of relay R4.If during the interval in which the acceptance means prevents transferof the signal from core C4 to the utilization means, a new input signalis applied to the transfer circuit and a new trigger pulse is alsoapplied to the circuit, the signal is transferred from core C1 to coreC2 and then to core C3, in a manner similar to that previously eX-plained. However, when the signal reaches core C3, setting the core andthereby energizing relay R6, minor aperture 3 of core C3 becomes primedand relay R3 closes its front contact 20. Since core C4 is set, relay R7is energized, thereby maintaining relay R4 energized. Front contact 40of relay R4 is therefore open, preventing capacitor 36 from dischargingthrough front contact 20 of relay R3, thereby preventing core C3 frombecoming cleared. Thus, a first bit of information is stored in core C4,and a second bit of information is stored in core C3.

In the event still another input signal is applied to the transfercircuit, it can travel only as far as core C2, which then becomes set;however, for reasons similar to those previously explained, capacitor 35cannot discharge through front contact 19 of relay R2, therebypreventing core C2 from becoming cleared. If still another input signalreprcsentative of another bit of information is applied to the transfercircuit, core C1 will become set and will be prevented `from clearingthrough capacitor 34 because back contact 38 of relay R2 is now open.

If now acceptance means 46 should momentarily complete a circuit betweencapacitor 37 and front contact 21 of relay R4, core C4 becomes cleared,thereby coupling the information stored therein to utilization means 45.Upon clearing of core C4, relay R7 deenergizing relay R4. This closesback contact 40 of relay R4, permitting capacitor 36 to dischargethrough front contact 20 of relay R3 and clear core C3 through its majoraperture, transferring information from core C3 to core C4. Likewise,back contact 39 of relay R3 then closes, permitting capacitor 35 todischarge through front contact 19 of relay R2 and clear core C2,thereby setting core C3. This in turn permits capacitor 34 to dischargethrough back contact 38 of relay R2 and front contact 18 of relay R1,thereby clearing core C1 and causing it to transfer its information tocore C2. Core C1 is now clear and prepared to accept a new bit ofinformation.

If the acceptance means again completes a circuit between capacitor 37and front contact 21 of relay R4, core C4 again produces an outputpulse, and information stored in core C3 is transferred to core C4,while information stored in core C2 is transferred to core C3. Thus,each core and the relays coupled thereto function as a separate bufferstorage stage in the signal transfer circuit.

Turning now to FIG. 3 there is shown a modification of the circuit ofFIG. 2, wherein back transfer of core output pulses is prevented byutilization of a separate input aperture in each of the cores and bycoupling prime current through each input aperture in order to slowlyswitch flux direction in the core leg outside the input aperture priorto clearing the core, thereby preventing a sharp flux direction changein that leg which could induce a voltage in a set winding coupledthereon. Thus, the transfer circuit of FIG. 3 shows use of fourmultiaperture cores C11-C14, for storage of information. Each Core hasan input minor aperture 61, 63, 65 and 67, respectively, and an outputmirror aperture 62, 64, 66 and y68, respectively. Cores C12-C14 moreoverhave third minor apertures 69-71, respectively, for producing radiofrequency energy indicative of the remanent magnetic state of the core.Driver relay R11-R14 are connected in a fashion similar to drive relaysR1-R4 of FIG. 2, with the exception that energization current for eachdriver relay is coupled through both input and output minor apertures ofthe core with which the relay is associated. This current serves toprime both minor apertures through which it is coupled.

Operation of this circuit is quite similar to that of the circuit ofFIG. 2. Here however, when a signal is applied to the circuit inputterminals, core C11 becomes set by passage of input current throughminor aperture 61. When relay R11 is 'thereafter triggered, a signal iscoupled from output minor aperture 62 of core C11 to input minoraperture 63 of core C12, thereby setting core C12. In a manner similarto that explained in conjunction with FIG. 2, relay R12 then becomesenergized, coupling prime current through minor apertures 63 and 64 ofcore C12. When a clear pulse is thereafter passed through the majoraperture of core C12, an output pulse is coupled from minor aperture 64of core C12 to input minor aperture 65 of core C13, setting core C13.Since magnetic flux direction in the core leg outside minor aperture 63of core C12 has previously been switched slowly by current ow throughrelay R12, no back pulse is coupled from minor aperture 63 of core `C12to minor aperture 62 of core C11. This is because relay R12 addsinductance to the prime circuit, thereby preventing sudden changes ofprime current through the minor apertures of the core to which it iscoupled. Similar eifects are produced on cores C13 and C14 by relays R13and R14, respectively. The remainder of operations performed by thecircuit FIG. 3 are performed in identical fashion with the operationsperformed by the circuit of FIG. 2.

Turning next to FIG. 4, there is shown a signal transfer circuit whereineach storage means comprises a column of apertured magnetic cores, andis therefore capable of storing a large number of Ibits of information.Driving circuits for priming and clearing the cores in FIG. 4 areidentical to the driving circuits shown in FIG. 2. The circuitaccommodates a plurality of inputs and provides a plurality of outputs.

The circuit is shown having four inputs, input l-input 4. Not everyinput must receive a signal, since a composite signal may be applied tothe circuit wherein presence or absence of a pulse is used to denoteinformation, that is, a pulse code modulated signal can be applied tothe circuit instead of merely a single pulse.

The final storage means in this embodiment of the circuit are connectedso as to provide additional output information in accordance with theinput code. To achieve this result, each core of the fourth column ofcore utilizes two output minor apertures. Thus, core C400 has a pair ofoutput minor apertures and 101, core C401 has Ia pair of output minorapertures 102 and 103, core C402 has a pair of output minor apertures104 and 105, and core C403 has a pair of output minor apertures 106 and107. Each of the aforementioned cores also utilizes a separate inputminor aperture, 10S-111, respectively. Relay R7 is coupled through aminor aperture 112 of core C400 for energization by radio frequencyenergy from a signal generator 8 when core `C400 is set.

Acceptance means are herein shown, for illustrative purposes, as a relayR9 having a front contact 114. This contact provides current throughfront contact 21 of relay R4 and either front or back Contact 115 of adirection control relay R8, depending upon whether relay R8 is energizedor deenergized from an external terminal 113, through the output minorapertures of cores C400-C403. Thus, when front contacts 114 and 21 areclosed, if relay R8 is deenergized, output minor apertures 101, 103, 105and 107 of cores C400-C403, respectively, are primed, while if relay R8is energized, minor apertures 100, 102, 104 and 106 of cores C400-C403,respectively, are primed. Thus, upon deenergization of relay R8, outputs1R, 2R, 3R, and 4R provide output information, while when relay R8 isenergized, outputs 1N, 2N, 3N and 4N provide output information.

A relay R10 is coupled to the prime windings of cores G400-C403. Whenrelays R9 and R4 are both energized, relay R10 is energized throughfront contacts .114 and 21. Front contact 116 of relay R10 then closes,causing discharge of capacitor 37 through the major apertures of coresC400-C403, thereby providing readout of the final stage of the circuit.

Energization for relay R4 is here used to prime only the input minorapertures 108-111 of cores C400C403, respectively, in order to avoidback transfer of pulses from the aforementioned cores upon clearing ofthe cores.

In operation, assume a pulse code modulated signal is applied to inputs1-4 such that, for example, input 1,

input 3 and input 4 each receives a pulse while input 2 receives nopulse. Thus, cores C100, C102 and C103 are set, while core C101 remainsclear. When a trigger signal is thereafter applied t relay R1, outputminor Iapertures 117, 119 and 120 of cores C100, C102 and C103 becomesprimed. Closing of front contact 18 of relay R1 then causes capacitor 34to discharge through the major apertures of cores C100-C103, providingreadout from these cores. This causes cores C200, C202 and C203 tobecome set, while core C201 remains clear. Rel-ay R5 then causesenergization of relay R2, and the information stored in cores C200-C203is transferred to cores C300-C303, respectively, when capacitor 35discharges through front contact 19 of relay R2, clearing coresC200-C203. This causes cores C300, C302 and C303 to become set, whilecores IC301 remain clear.

Upon setting of core C300, relay R6 energizes, causing relay R3 toenergize and close its front contact 20. This causes discharge ofcapacitor 36 through front contact 20 of relay R3 and the majorapertures of cores C300 C303, causing transfer of set pulses from coresC300, C302 and C303 to cores C400, C402 and C403, respectively. Sincecore C400 is now set, relay R7 energizes, causing relay R4 to energizeand close its front contact 21. Moreover, if relay R8 is energized,closing its front contact 115, and if the acceptance input terminals ofrelay R9 are energized, front contact 114 of relay R9 closes and minorapertures 100, 104 and 106 of cores C400, C402 and C403 respectivelybecome primed. Furthermore, relay R10 becomes energized, closing itsfront contact 116. This causes discharge of capacitor 37 through themajor apertures of cores G400-C403, producing the applied pulse codemodulated signal on outputs 1N-4N, whereby output 1N, output 3N andoutput 4N each provide an output voltage and output 2N provides nooutput voltage.

If the acceptance input terminals of relay R9 are not energized, contact114 of relay R9 is open, preventing priming of the output minorapertures of cores C400- C1403 and preventing energization of relay R10,thereby also preventing discharge of capacitor 37 through front contact116 of relay R-10. Under these circumstances, a signal applied to thecircuit travels as far as cores C400- C403 and then remains stored inthe aforementionad cores until the acceptance input terminals of relayR9 are energized, providing readout of the signal.

In the event the acceptance input terminals of relay R9 are notenergized and a pulse code is stored in cores C400-C403, then, if asecond input code is applied to inputs 1-4, the incoming coded signal istransferred from cores C100-C103 to cores C200-C203 and thence to coresC300-C303, wherein it is stored. The signal cannot be transferred fromcores C300-C303 since relay R4 is energized through front contact 17 ofrelay R7, thereby holding open its back contact 40, preventing capacitor36 from discharging through the major apertures of cores C300-C303. Inlike fashion, a third coded signal can be stored in cores C200-C203 anda fourth coded signal can be stored in cores C100-C103.

In the event a signal stored in cores G400-C403 is transferred out byenergization of relay R9, relay R7 deenergzes, deenergizing relay R4 andpermitting back contact 40 of relay R4 to close. This permits capacitor36 to discharge through the major apertures of cores C300- C303, therebytransferring the signal stored in the third storage means to coresG400-C403. Likewise, the code stored in the second storage means is thentransferred to the third storage means upon discharge of capacitor 35through the major apertures of cores C200-C203, and the coded signalstored in the first storage means is transferred to the second storagemeans upon discharge of capacitor 34 through the major apertures ofcores C100L C103.

Assuming the acceptance input terminals of relay R9 remain energized,assume the signal now stored in the fourth storage means is coded sothat core C403 is clear while cores G400-C402 are set. Assume furtherthat relay R8 is deenergized, thereby closing its back contact 115. Whenrelay R4 energizes, its front contact 21 closes, priming minor apertures101, 103 and 105 of cores C400, C401 and C402. This causes energizationof relay R10, which closes its front contact 116, thereby clearing coresC400-C403. A coded output signal then appears on outputs 1R-4R, andcomprises a voltage pulse on outputs 1R, 2R and 3R, and no voltage pulseon output 4R.

Thus, there has been shown a signal transfer circuit comprising aplurality of storage stages whereby information is automaticallytransferred from one stage through a subsequent clear stage, until itreaches the circuit output terminals or a clear storage stage just priorto a stage retaining stored information, in which case it is stored inthe clear stage until the information stored in the next subsequentstage is transferred ahead. The circuit utilizes separate driverscoupled to each separate storage stage for sensing the condition of anext subsequent storage stage and driving information from the stage inwhich it is stored into the next subsequent storage stage only when thenext subsequent stage is clear. Moreover, the driver circuits are simpleand utilize few circuit components; yet each is responsive to theremanent magnetic state of the next subsequent core, so as to prevent anattempt at transfer of stored information from one core to a subsequentcore which it already set and therefore unable to accept a new setpulse.

Although several embodiments of the present invention have beendescribed, it is to be specifically understood that these forms areselected to facilitate in disclosure of the invention rather than tolimit the number of forms which it may assume; various modifications andadaptations may be applied to the specific forms shown to meetrequirements of practice, without in any manner departing from thespirit or scope of the invention.

What is claimed is:

1. A signal transfer circuit comprising a plurality of storage means,each said means being coupled to a subsequent storage means, and aseparate driver circuit coupled to each storage means and responsive toinformation stored in the next subsequent storage means for drivinginformation into the next subsequent storage means.

2. The circuit of claim -1 wherein the storage means comprises aplurality of apertured magnetic cores.

3. A circuit for controlling passage of a signal therethrough inaccordance with circuit conditions comprising a plurality of aperturedmagnetic cores, each core having an input and an output, means couplingthe output of each core to the input of a subsequent core, a separatedriver circuit coupled to each core for clearing said cores, and meanscoupling each driver circuit to each subsequent core for controllingoperation of said driver in response to the remanent magnetic state ofsaid subsequent core.

4. A signal transfer circuit comprising at least a pair of aperturedmagnetic cores, each core having an input and an output, means couplingthe output of a first core of said pair to the input of the second coreof said pair, means coupling an input signal to the first core, meanscoupling an output signal from the second core, switching means coupledto said pair and responsive to the remanent magnetic state of each coreof said pair, and energy storage means coupled to the switching meansfor providing a clear pulse through the first core only when the firstcore is set and the second core is clear.

5. A circuit for controlling passage of a signal therethrough inaccordance with circuit conditions comprising a plurality of aperturedmagnetic cores, each core having an input and output, means coupling theoutput of each core to the input of a subsequent core, switching meanscoupled to each pair of adjacent cores and responsive to the remanentmagnetic state of each prior and subsequent core of said pair, andenergy storage means coupled to the switching means for providing aclear pulse through the prior core of said pair when said prior core isset and the subsequent core of said pair is clear.

6. A circuit for controlling passage of a signal therethrough inaccordance with circuit conditions comprising a plurality of aperturedmagnetic cores, each of said cores having input means and output means,means coupling the output means of each separate core to the input meansof a subsequent core, and driver means responsive to the remanentmagnetic state of each said subsequent core for clearing each saidseparate core and thereby transferring information to the subsequentcore only when the subsequent core is clear.

7. The circuit of claim 6 wherein the driver means for clearing saidseparate core comprises a first relay, means responsive to the remanentmagnetic state of said separate core for controlling energization of therelay, energy storage means, a second relay coupled to said subsequentcore, and means coupling clear current through said separate -core fromsaid energy storage means through a front contact of the first relay anda back contact of the second relay.

8. The circuit of claim 7 wherein energization current for the rst relayis coupled to said separate core for priming said output means.

9. The circuit of claim 7 wherein the means responsive to the remanentmagnetic state of said -separate core comprises a relay coupled to saidseparate core and having a front contact coupled to the first relay forenergizing said first relay when said separate core contains storedinformation.

10. The circuit of claim 9 wherein energization current for the firstrelay is coupled to said separate core for priming said output means.

11. Driver means for a circuit having a plurality of apertured magneticcores coupled to transfer a signal from one core to a subsequent corecomprising a plurality of first relays, means responsive to the remanentmagnetic state of each separate core for energizing each of said relays,energy storage means, and means coupling a clear pulse for said one corefrom said energy storage means through a back contact of the relayenergized from the subsequent core and a front contact of the relayenergized from said one core for clearing said one core only when saidsubsequent core is in the clear condition.

12. The driver means of claim 11 wherein each responsive means comprisesa second relay coupled to each separate core and having a front contactcoupled to the rst relay energized from said separate core wherebypresence of information stored in the separate core produces actuationof the second relay energized from said core.

13. Driver means for a circuit having a plurality of columns ofapertured magnetic cores coupled to transfer a signal from one column toa subsequent column comprising a plurality of first relays, meansresponsive to the remanent magnetic state of the first core in eachcolumn for energizing each of said relays, energy storage means, andmeans coupling a clear pulse for a single column from said energystorage means through a back contact of the relay energized from thefirst core of the subsequent column adjacent said single column and afront contact of the relay energized from the first core of said singlecolumn for clearing the cores of said single column only when the firstcore in said subsequent adjacent column is in the clear condition.

14. The driver means of claim 13 wherein each responsive means comprisesa second relay coupled to the first core in the single column and havinga front contact coupled to the first relay energized from the first corein said single column whereby presence of information stored in thefirst core of the single column produces actuation of the second relayenergized from the first core of said single column.

15. A circuit for controlling passage of a signal therethrough inaccordance with circuit conditions comprising a plurality of columns ofapertured magnetic cores, each core having an input and an output, meanscoupling the output of each core to the input of a subsequent core, aseparate driver circuit coupled to the cores in each column for clearingthe cores of said column, and means coupling each driver circuit to onecore in each subsequent column of cores for controlling operation ofsaid driver in response to the remanent magnetic state of said one core.

16. A circuit for controlling passage of a signal therethrough inaccordance with circuit conditions comprising a plurality of columns ofapertures magnetic cores, each column having an input and an output,means coupling the output of each column to the input of a subsequentcolumn, a separate driver circuit coupled to each column for producingtransfer of information out of said column, and means coupling eachdriver circuit to each subsequent column for controlling operation ofsaid driver in response to information stored in said subsequent column.

17. A method of transferring information signals through seriallycoupled storage means to a utilization circuit comprising the steps ofsetting a first storage means with the information signal, successivelysetting each subsequent storage means in accordance with the informationsignal stored in each prior adjacent storage means only when informationstored in the subsequent storage means is cleared, and finallytransferring the information signal from the last storage means wheneverthe utilization circuitry is capable of accepting such informationsignal.

18. The method of claim 17 wherein the storage means comprisemultiaperture magnetic cores.

References Cited UNITED STATES PATENTS 3,114,897 12/1963 Way Dong Woo340--174 JAMES W. MOFFITT, Primary Examiner.

U.S. Cl. X.R.

